1. Technical Field
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having a processor reset function.
2. Description of Related Art
In general, a semiconductor memory device having multiple access ports is called a multiport memory. More particularly, a memory device having two access ports is called a dual-port memory. A typical dual-port memory may be an image processing video memory having a random access memory (RAM) port accessible in a random sequence and a serial access memory (SAM) port accessible only in a serial sequence.
A multipath accessible semiconductor memory device is distinguishable from a multiport memory. Unlike the configuration of the video memory, a multipath accessible semiconductor memory device includes a dynamic random access memory (DRAM), which has a shared memory area accessible by respective processors through multiple access ports. A memory cell array of the device does not have a SAM port, but is constructed of DRAM cells.
Universally, remarkable developments are being made in consumer electronic systems. For example, in recent mobile communication systems, such as handheld multimedia players, handheld phones, PDAs, etc., manufacturers are producing products having multiprocessor systems, which incorporate processors adapted in one system to obtain higher speeds and smoother operations.
An example of a conventional memory adequate for a multiprocessor system is disclosed by MATTER et al. (U.S. Patent Application Publication No. 2003/0093628), published May 15, 2003. MATTER et al. generally discloses technology for accessing a shared memory area by multiple processors, in which a memory array includes first, second and third portions. The first portion of the memory array is accessed only by a first processor, the second portion is accessed only by a second processor, and the third portion is a shared memory area accessed by both the first and second processors.
In contrast, a general multiprocessor system has a nonvolatile memory that stores processor boot codes, e.g., a flash memory, for processors. A DRAM is also adapted as a volatile memory for every corresponding processor. That is, the DRAM and the flash memory are each adapted to one processor. The configuration of the processor system is therefore complicated and costly.
Therefore, a multiprocessor system adaptable to a mobile communication device was developed, as shown in FIG. 1. More particularly, FIG. 1 is a schematic block diagram of a conventional multiprocessor system having a multipath accessible DRAM.
As shown in FIG. 1, in a multiprocessor system including two or more processors 100 and 200, one DRAM 400 and one flash memory 300 are shared. Also, a data interface between processors 100 and 200 is obtained through the multipath accessible DRAM 400. In FIG. 1, the first processor 100, which is not directly connected to the flash memory 300, may indirectly access the flash memory 300 through the multipath accessible DRAM 400.
The first processor 100 may have an application function of performing a predetermined task. For example, the first processor 100 may provide user applications, such as data communications, electronic games or amusement, etc. The second processor 200 may have a MODEM function, for example, to perform modulation/demodulation of communication signals. However, the respective functions of the processors may vary.
The flash memory 300 may be a NOR flash memory having a NOR structure for a cell array configuration, or a NAND flash memory having a NAND structure for a cell array configuration. The NOR flash memory or the NAND flash memory is a nonvolatile memory for which memory cells, e.g., constructed of MOS transistors having floating gates, are formed in an array. Such nonvolatile memory stores data that is not deleted, even when power is turned off, such as boot codes of handheld instruments, preservation data, and the like.
In addition, the multipath accessible DRAM 400 functions as a main memory for a data process of the processors 100 and 200. As shown in FIG. 1, first and second ports 60 and 61, respectively connected to corresponding system buses B1 and B2, are inside the multipath accessible DRAM 400, so that the multipath accessible DRAM 400 may be accessed by the first and second processors 100 and 200 through two different ports. The multiple port configuration differs from a general DRAM configuration having a single port.
In the multipath accessible DRAM 400, four memory areas 10, 11, 12 and 13 constitute a memory cell array. For example, memory area 10 (bank A) may be accessed exclusively by the first processor 100 through the first port 60, and memory areas 12 and 13 (banks C and D) may be accessed exclusively by the second processor 200 through the second port 61. The memory area 11 (bank B) may be accessed by both the first and second processors 100 and 200 through first and second ports 60 and 61 as different ports. As a result, in the depicted memory cell array, bank B is a shared memory area, and banks A, C and D are dedicated memory areas, accessible only by one corresponding processor. The four memory areas 10-13 (banks A-D) may be constructed as a bank unit of the DRAM 400. Each bank may have memory storage of 64 Mb, 128 Mb, 256 Mb, 512 Mb or 1024 Mb, for example.
In the multiprocessor system of FIG. 1, the DRAM 400 and the flash memory 300 can be used in common without having to be assigned to every processor. Therefore, the system is less complicated and thus smaller, and the number of memories can be reduced.
The multipath accessible DRAM 400 shown in FIG. 1 is similar in functionality to a DRAM type memory known as OneDRAM™, provided by Samsung Electronics Co. Ltd. OneDRAM™ is a fusion memory chip that increases data processing speed between a communication processor and a media processor in a mobile device. In general, two processors require two memory buffers. However, the OneDRAM™ solution can route data between processors through a single chip, so two memory buffers are not required. OneDRAM™ reduces data transmission time between processors by employing a dual-port approach. A single OneDRAM™ module can replace at least two mobile memory chips, e.g., within a high-performance smart-phone or other multimedia rich-handset. As data processing speed between processors increases, OneDRAM™ reduces the number of chips, reduces power consumption by about 30 percent and reduces total die area coverage by about 50 percent. As a result, cellular phone speed may increase five times, battery life may be prolonged, and handset design may be slimmer, for example.
In a multiprocessor system sharing one flash memory and a multipath accessible DRAM, such as OneDRAM™, etc., boot codes of all processors, e.g., the processors 100 and 200, are stored in the flash memory 300. The second processor 200 directly accesses the flash memory 300 and starts initial booting of the system. However, the first processor 100, which is indirectly connected to the flash memory through a DRAM interface, cannot promptly read its boot code. Therefore, when boot time ends, the first processor 100 may have a halt state in operation due to the prolonged read time.
In initial booting, therefore, the second processor 200, determined to be a master processor, applies a reset signal RESET to a reset pin of the first processor 100, determined to be a slave processor, using a host interface, thereby controlling the booting of the slave processor 100. That is, according to the structure indicated by FIG. 1, the master processor 200 starts its own booting and also applies a reset enable signal to the slave processor 100 through host interface line 202. Then, when the master processor 200 has completed booting, the master processor 200 applies a reset disable signal to the slave processor 100 in order to disable the reset signal that was applied to the slave processor 100. The slave processor 100 starts booting upon receipt of the reset disable signal.
The reset control described above requires reset line 202 connected between the processors and the reset to be performed through a host interface between the processors. Thus, the master processor 200 must keep controlling the reset of the slave processor 100 during system booting. Furthermore, there must be both a DRAM interface and a host interface in the multiprocessor system, which reduces operating speed. Thus, improved reset control for initial booting of a multiprocessor system is needed.
Accordingly, embodiments of the invention provide a semiconductor memory device capable eliminating the need for boot time control over a slave processor during initial booting of a system, and avoiding a halt state of operation in the slave processor. Also, a reset signal line between multiple processors is not needed. Embodiments may provide a DRAM, e.g., a OneDRAM™, having a processor reset function and a processor reset control method.
According to an embodiment of the invention, a semiconductor memory device is provided for use in a multiprocessor system. The semiconductor memory device includes a shared memory area and a reset signal generator. The shared memory area is accessible by processors of the multiprocessor system through different ports, the shared memory area being assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the plurality of processors, for a predetermined time after an initial booting of the multiprocessor system, and to provide a reset disable signal to the slave processor after the predetermined time lapses.
The reset enable signal may be generated in the semiconductor memory device, and the reset disable signal may be generated in the semiconductor memory device under control of a processor, predetermined as a master processor among the multiple processors.
The semiconductor memory device may include a DRAM type memory used in common by the processors, and the multiprocessor system may include a nonvolatile semiconductor memory device for storing a boot code. The reset signal generator may include an externally controllable mode register set circuit or extended mode register set circuit. Also, the reset enable signal and the reset disable signal may be generated in the semiconductor memory device.
The reset signal generator may include a mode register set circuit configured to output a register setting signal in response to an external signal; a latch configured to latch the register setting signal applied through an input node; a switching transistor configured to discharge the input node in response to a power-up reset related signal; and a driver configured to drive an output signal of the latch and to output the output signal as one of the reset enable signal or the reset disable signal. The reset signal generator may include a power voltage sensing unit configured to sense a source voltage in the initial booting of the multiprocessor system, and to output a power-up reset related signal; an address signal level sensing unit configured to sense a level of an address signal output through an address buffer, and to output an operation state signal; a gating unit configured to gate the power-up reset related signal and the operation state signal, and to output a gating output signal; and a signal output unit configured to drive the gating output signal of the gating unit, to delay the power-up reset related signal and to drive the delayed power-up reset related signal in order to internally generate one of the reset enable signal or the reset disable signal.
The semiconductor memory device may further include an internal register accessible in response to an address of the shared memory area to provide an interface function among the processors. The internal register may be located outside the memory cell array. The memory cell array may further include dedicated memory areas, each dedicated memory area being accessible by one processor of the multiple processors.
According to another embodiment of the invention, a multiprocessor system includes at least two processors, a nonvolatile semiconductor memory and a semiconductor memory device. Each processor is configured to perform a predetermined task, and at least one of the processors is predetermined to be a slave processor. The nonvolatile semiconductor memory is connected to one of the processors, and stores boot codes corresponding to the processors. The semiconductor memory device includes a shared memory area, assigned to a portion of a memory cell array, and a reset signal generator. The shared memory area provides a data interface operation between the processors and is accessible in common by the processors through different ports. The reset signal generator provides a reset enable signal to the slave processor for a predetermined time after an initial booting of the system and provides a reset disable signal to the slave processor after the predetermined time lapses.
The nonvolatile semiconductor memory device may include a NAND flash memory. Also, at least one of the processors may be predetermined to be a master processor, where the reset enable signal is generated in the semiconductor memory device and the reset disable signal is generated in the semiconductor memory device under control of the master processor.
The reset signal generator may include an externally controllable mode register set circuit or extended mode register set circuit. The reset enable signal and the reset disable signal may be generated in the semiconductor memory device.
The reset signal generator may include a mode register set circuit for outputting a register setting signal in response to an external signal; a latch for latching the register setting signal applied through an input node; a switching transistor for discharging the input node in response to a power-up reset related signal; and a driver for driving an output signal of the latch and outputting the output signal as the reset enable signal or reset disable signal. The reset signal generator may include a power voltage sensing unit for sensing a source voltage in the initial booting of the system, and outputting a power-up reset related signal; an address signal level sensing unit for sensing a level of address signal output through an address buffer, and outputting an operation state signal; a gating unit for gating the power-up reset related signal and the operation state signal, and outputting a gating output signal; and a signal output unit for driving the gating output signal of the gating unit, delaying and driving the power-up reset related signal, thereby generating the reset enable signal or reset disable signal without assistance from an external processor.
According to another embodiment of the invention, a method is provided for controlling processor reset during an initial booting of a multiprocessor system, including first and second processors, a nonvolatile semiconductor memory and a volatile semiconductor memory, and for performing a data interface of the first and second processors through the volatile semiconductor memory. The method includes applying a reset enable signal, generated through a reset pin of the volatile semiconductor memory, to the first processor for a time period after the initial booting of the multiprocessor system starts, during which a booting operation of the second processor is performed; and applying a reset disable signal through the reset pin of the volatile semiconductor memory after the booting operation of the second processor is completed, the reset disable signal releasing the reset enable signal to the first processor and enabling a booting operation of the first processor to be performed without a halt caused by a boot time-over.
The reset enable signal may be generated in the volatile semiconductor memory device, and the reset disable signal may be generated under control of the second processor by a mode register set circuit. Alternatively, the reset disable signal may be generated in the volatile semiconductor memory device in response to a state of power-up reset related signal.
In the device and method according to various embodiments, a boot time-over of a processor can be prevented during an initial booting of a multiprocessor system, thus avoiding a halt state in the processor operation. In addition, a reset of the processor may be performed rapidly by a reset enable signal generated in a semiconductor memory device itself, a reset signal line between processors is not needed, and a reset of the processor may be controlled by a multipath accessible semiconductor memory device.